1. Field of the Invention
The present invention relates to semiconductor fabrications, and in particular relates to methods for forming patterns.
2. Description of the Related Art
Lithography beyond the 45 nm node faces numerous challenges. The challenges are associated with the use of photoresists to define sub-40 nm features, including line-edge roughness, shot noise, acid diffusion blur, and resist collapse. The use of ionizing radiation such as extreme ultraviolet radiation, X-rays, ion beams or electron beams pose additional concerns such as surface charging and contamination.
In light of such difficulties, double patterning has recently emerged as a way to proceed to the 32 nm half-pitch node. In such an approach, two critical lithographic exposures are required. The second exposure must be critically aligned to insert new features between previously exposed features. Thus, this adds a potential source of yield loss, and adds an extra cost for the second photolithographic step.
Other methods for producing fine pitch patterns have been disclosed. A form of double patterning which does not require a second critical exposure uses sidewall spacer formation to effectively achieve feature doubling. This approach is described for example in “Fabrication of Sub-10 nm Silicon Nanowire Arrays by Size Reduction Lithography” by Choi et. al. (J. Phys. Chem B. 107, 3340-3343 (2003)). However, the method is potentially limited by lack of selectivity between the spacer material and the underlying substrate, but more significantly cannot prevent the erosion at the top of the spacer during etching. This results in a tapered tip profile which could affect dimensional control during deposition and etching.
In the U.S. Pat. No. 5,795,830, “Reducing pitch with continuously adjustable lines and space dimensions”, feature spacing is reduced by oxidizing a portion of pre-existing polysilicon lines, then depositing conformal oxide. Removing the polysilicon after etching back the conformal oxide cover results in a shrink of the space in-between features. This however, does not allow generation of regular arrays of features, and the tapered profile of the etched back oxide is still an issue.
In the U.S. Pat. No. 5,918,132, “Method for narrow space formation and self-aligned channel implant”, spacer material and hard mask material are deposited on a previously defined hard mask, and planarization is used to produce a narrower spacer separating the first and second hard mask materials. The spacer is then etched away, leaving a narrow groove separating the first and second materials. This method is applied only to produce a single isolated narrow groove, and not designed to produce an array of dense features.
There is therefore a need for new methods of forming ultrafine patterns.